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Author:
None
License:
MIT
Summary:
Parse, analyze, simulate, and generate Verilog/SystemVerilog from Python.
Latest version:
0.0.7
Required dependencies:
intervaltree
|
lark
|
pygls
|
rich
|
treelib
Optional dependencies:
cython
|
filelock
|
myhdl
|
pre-commit
|
pytest
|
pytest-cov
|
pytest-xdist
|
setuptools
|
vulture
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