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Author:
Ben Reynwar
License:
MIT
Summary:
Utilities for generating VHDL to convert to and from std_logic_vector, as well as utilties to create testbenches described by python.
Latest version:
0.5.0
Required dependencies:
cocotb
|
fusesoc
|
jinja2
|
pytest
|
pyyaml
|
vunit-hdl
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